1. Field of the Invention
The present invention relates to an address decoder, a semiconductor memory comprising the address decoder and a semiconductor device comprising at least one of a logical product circuit, a logical add circuit and an inverter circuit.
2. Description of the Related Art
A semiconductor memory represented by a RAM (Random Access Memory) and a ROM (Read Only Memory) comprises a row decoder and a column decoder for selecting a desired memory cell within a memory cell array provided therein. A conventional semiconductor memory of this type will be described with reference to FIG. 9. It is noted that, however, for brevity, FIG. 9 illustrates a memory cell array 10 having provided therein 8.times.8=64 memory cells (not shown).
The semiconductor memory comprises a memory cell array 10, a row decoder 30, a column decoder 50 and a sense amplifier 70. The row decoder 30 has terminals CL0 to CL7 connected to the memory cell array 10. The column decoder 50 has terminals R0 to R7 connected to the memory cell array 10 and a terminal 51 connected to the sense amplifier 70. The row decoder 30 and the column decoder 50 are thus connected to the memory cell array 10 through the terminals CL0 to CL7 and the terminals R0 to R7, respectively. The column decoder 50 is also connected to the sense amplifier 70 through the terminal 51.
When this semiconductor memory is used, first address designation signals A0 to A2 of three bits are inputted into the column decoder 50. Second address signals A3 to A5 of three bits are inputted into the row decoder 30. Then, depending on logical levels of respective bits of the first address designation signals A0 to A2, one of the terminals R0 to R7 of the column decoder 50 is selected. Depending on logical levels of respective bits of the second address designation signals A3 to A5, one of the terminals CL0 to CL7 of the row decoder 30 is selected. As a result, a memory cell positioned at an intersection (or crossover point) between a column selected by one bit signal among the first address designation signals A0 to A2 and a row selected by one bit signal among the second address designation signals A3 to A5, is selected.
A row decoder and a column decoder having structures described below are examples of the above-stated conventional row decoder 30 and column decoder 50.
An example of the structure of the row decoder 30 will be now described. FIG. 10 is a circuit diagram showing the inner structure of the row decoder 30.
The row decoder 30 comprises a first signal line group 31, a second signal line group 33, a plurality of switching devices 35, pull-up resistors 37, output inverters 39.sub.0 to 39.sub.7 and input logic adjustment inverters 41.sub.0 to 41.sub.5.
The first signal line group 31 consists of six parallel signal lines 31.sub.0 to 31.sub.5. The signal A3 out of the three address designation signals A3 to A5 is inputted into a signal line 31.sub.1 in the first signal line group 31. The signal A4 is inputted into a signal line 31.sub.3. The signal A5 is inputted into a signal line 31.sub.5. A signal A3 opposite in phase to the signal A3 is inputted into a signal line 31.sub.0 in the first signal line group 31. A signal A4 opposite in phase to the signal A4 is inputted into a signal line 31.sub.2, and a signal A5 opposite in phase to the signal A5 is inputted into a signal line 31.sub.4. Here, a signal of opposite phase such as A3 is at L (or H) level when a signal A3 is at H (or L) level.
To realize the input of address designation signals as described above, the signal A3 is inputted into the signal line 31.sub.1 through the inverters 41.sub.0 and 41.sub.1, and the output of the inverter 41.sub.0 is inputted as the signal A3 into the signal line 31.sub.0. The signal A4 is inputted into the signal line 31.sub.3 through the inverters 41.sub.2 and 41.sub.3, and the output of the inverter 41.sub.2 is inputted as the signal A4 into the signal line 31.sub.2. Moreover, the signal A5 is inputted into the signal line 31.sub.5 through the inverters 41.sub.4 and 41.sub.5, and the output of the inverter 41.sub.4 is inputted as the signal A5 into the signal line 31.sub.4.
The second signal line group 33 consists of eight parallel signal lines 33.sub.0 to 33.sub.7. The second signal line group 33 is arranged to intersect the first signal line 31. It is noted that, in actuality, the second signal lines 33.sub.0 to 33.sub.7 include switching devices 35, respectively and an impurity diffused layer formed on a semiconductor substrate (see FIG. 11(B)), which description will be given below.
Each of the switching devices 35 is provided in the vicinity of a plurality of predetermined intersections among intersections (or crossover points) P between the first signal line group 31 and the second signal line group 33, although only part of the intersections are denoted by P in FIG. 10. The intersections will be described later.
Each of the switching devices 35 has a control signal input terminal 35a. The switching device 35 can be made out of an enhancement type P-channel or N-channel field effect transistor. In FIG. 10, the switching devices 35 consist of enhancement type N-channel field effect transistors, respectively. The control signal input terminal (or, to be specific, a gate electrode) 35a of each switching device 35 is connected to a first signal line closest to the corresponding intersection. The switching device 35 per se is connected, in series, to a second signal line closest to the intersection. Specifically, each switching device 35 is connected to the second signal line through a drain serving as a first main electrode and a source serving as a second main electrode. (See FIG. 11(B) for more detailed illustration.)
In this case, the predetermined intersections, i.e. crossover points in the vicinity of which the switching devices 35 are provided, are set as follows. Assume that a value m which is one of values 0 to 7 in decimal notation is defined as address designation signals A3 to A5. In the conventional row decoder 30, switching devices 35 are provided such that when the value m is inputted into the first signal line group 31, the provided switching devices 35 become conductive and a m-th second signal line, that is, second signal line 33.sub.m corresponding to the value m in the decimal notation out of the signal lines 33.sub.0 to 33.sub.7 in the second signal line group 33) turns into a first electric state (a conductive state in this case).
More specifically, in the prior art of FIG. 10, in respect of the 0-th signal line in the second signal line group 33 or signal line 33.sub.0, the switching devices 35 are provided in the vicinity of intersections between the second signal line 33.sub.0 and the first signal line 31.sub.0, 31.sub.2 and 31.sub.4, respectively. Due to this, when (0, 0, 0) (corresponding to "000" in the binary notation), that is, m=0 (in the decimal notation) is inputted as address designation signals A3, A4 and A5, respective switching devices 35 in the vicinity of the above intersections are turned on and other switching devices 35 provided in the vicinity of the intersections between second signal lines other than the 0-th signal 33.sub.0 and the first signal lines 31.sub.0, 31.sub.2 and 31.sub.4 are turned off, respectively. As a result, only the 0-th signal line 33.sub.0 in the second signal line group 33 is selectively conductive. As regards, for example, the 7th signal line 33.sub.7 in the second signal line group 33, switching devices 35 are provided in the vicinity of intersections between the second signal line 33.sub.7 and the first signal lines 31.sub.1, 31.sub.3 and 31.sub.5, respectively. Due to this, when (1, 1, 1) (corresponding to "111" in the binary notation), that is, m=7 (in the decimal notation) is inputted as address designation signals A3, A4 and A5, the switching devices 35 in the vicinity of these intersections are turned on and other switching devices 35 provided in the vicinity of the intersections between second signal lines other than the 7th signal line 33.sub.7 and the first signal lines 31.sub.1, 31.sub.3 and 31.sub.5 are turned off, respectively. As a result, only the 7th signal line 33.sub.7 in the second signal line group 33 is selectively conductive.
In this way, in the conventional row decoder 30, if the value m is inputted as the address designation signals A3, A4 and A5, the signal line 33.sub.m corresponding to the value m becomes conductive. The relationship is shown in Table 1 below.
TABLE 1 ______________________________________ Signal line in first state Value m designated by A3-A5 (conductive state) among (A0-A2) signal lines 33.sub.0 to 33.sub.7 ______________________________________ 0 33.sub.0 1 33.sub.1 2 33.sub.2 3 33.sub.3 4 33.sub.4 5 33.sub.5 6 33.sub.6 7 33.sub.7 ______________________________________
The pull-up resistors 37 connect the signal lines 33.sub.0 to 33.sub.7 in the second signal line group 33 to the power supply V, respectively.
Input terminals of the output inverters 39.sub.0 to 39.sub.7 are connected to nodes between the second signal lines 33.sub.0 to 33.sub.7 and the pull-up resistors 37, respectively.
In the row decoder 30, when (0, 0, 0) is inputted as an address designation signal, the signal line 33.sub.0 in the second signal line group 33 turns into a conductive state based on the above-described principle while other signal lines 33.sub.1 to 33.sub.7 turn into a second electric state, that is, a non-conductive state. Due to this, the input terminal of the inverter 39.sub.0 becomes H level while input terminals of the remaining inverters 39.sub.1 to 39.sub.7 become L level. As a result, the terminal CL0 becomes H level and the terminals CL1 to CL7 become L level. Therefore, one of the terminals CL0 to CL7 (CL0 in this case) can be selectively made H level.
The following structure is typical of the actual structure of the row decoder 30 on and in the semiconductor substrate. Description will be given with reference to FIGS. 11(A) and (B). FIG. 11 is a plan view where a portion Q indicated by a broken line in FIG. 10 is emphatically shown. FIG. 11(B) is a cross-sectional view taken along lines I--I of FIG. 11(A). It is noted that FIG. 11(B) is a cross-sectional view where a section is emphatically illustrated.
In FIGS. 11(A), 11(B), reference numeral 35 denotes a gate insulating film of a field effect transistor 35; 42 a silicon substrate as a semiconductor substrate; 43 an impurity diffused region (source-drain region) in an active region; 45 an interlayer insulating film; and 45a a contact hole provided in the interlayer insulating film 45.
As can be understood from FIG. 11, in the actual structure, band-shaped active regions are formed in planned portions (including the impurity diffused region 43 in FIG. 11) for the formation of the second signal lines 33.sub.0 to 33.sub.7, respectively on the semiconductor substrate 42. The first signal lines 31.sub.0 to 31.sub.5 in the first signal line group 31 are constituted by part of a wiring or interconnecting member (on a first layer) provided on the interlayer insulating film 45. In addition, as can be, in particular, understood from FIG. 11(B), the signal lines (the signal line 33.sub.0 in FIG. 11(B)) in the second signal line group 33 are constituted by portions where part R of the wiring member on the first layer, the impurity diffused region 43 and the field effect transistors 35 are connected in series. In FIG. 11(B), while the three field effect transistors 35 are being turned on, the second signal line 33.sub.0 is conductive.
Meanwhile, a column decoder having a structure to be described below with reference to FIG. 12 is an example of the above-stated conventional column decoder 50. That is, it is an address decoder having a structure in which the pull-up resistors 37 and the output-side inverters 39.sub.0 to 39.sub.7 are removed from the constituent elements of the row decoder 30 described with reference to FIG. 10 and in which signals A0 to A2 are inputted as address designation signals.
In the column decoder 50, when a value m (where m=0 to 7) is inputted as the address designation signals A0 to A2, a signal line 33.sub.m in the second signal line group 33 becomes conductive and the remaining signal lines in the group 33 become non-conductive. Due to this, the signal line R.sub.m among the signal lines R0 to R7 in the column direction of the memory cell array 10 can be selected. The relationship between the value m indicated by the address designation signals A0 to A2 and the conductive signal line 33.sub.m can be expressed by truth values shown in Table 1 above.
However, in the conventional row decoder 30 and column decoder 50 mentioned above, the switching devices 35 are arranged regularly. Description will be given thereto below.
It is observed whether or not switching devices 35 are provided in the vicinity of intersections between the signal lines 31.sub.1, 31.sub.3 and 31.sub.5 in the first signal line group 31 and the signal lines 33.sub.0 to 33.sub.7 in the second signal line group 33, respectively. The observation is made from left to right, that is, from second signal lines 33.sub.0 to 33.sub.7 in the second signal line group 33 and from top to bottom in FIG. 10. Then, it is seen that no switching device is provided in the vicinity of three intersections between, for example, the signal line 33.sub.0 and the signal lines 31.sub.1, 31.sub.3, 31.sub.5, respectively. Such a state is expressed as (0, 0, 0). It is noted that `0` dignifies that a switching device 35 is not provided in the vicinity of an observed intersection while `1` dignifies that the device 35 is provided therein.
In case of three intersections (or crossover points) between the signal line 33.sub.1 and the signal lines 31.sub.1, 31.sub.3, 31.sub.5, respectively, a switching device 35 is provided in the vicinity of the intersection between the signal line 33.sub.1 and the signal line 31.sub.1 while no switching device 35 is provided in the vicinity of other two intersections. This state is (1, 0, 0). Likewise, states of the signal lines 33.sub.2 to 33.sub.7 are (0, 1, 0), (1, 1, 0), (0, 0, 1), (1, 0, 1), (0, 1, 1) and (1, 1, 1), respectively.
Namely, in the conventional row decoder 30 and column decoder 50, the switching devices 35 are arranged in a regular manner corresponding to the arrangement order of three bits in the binary notation. This produces a problem that the third party can easily analyze which signal line is conductive in the second signal line group 33 when address designation signals are inputted.
There is a case where the third party reads data within the memory cell array by using, for example, a probe and tries to misuse the data. To do so effectively, the third party may well first analyze which signal line is conductive in the second signal line group 33 when address designation signals are inputted.
It is of course possible to sequentially change address designation signals and to analyze which signal lines become conductive in the second signal line group in accordance with which address designation signals by using a probe one by one. However, consecutive analysis using a probe, if applied to a large-scale semiconductor memory, requires considerable time and labor. It is preferable for the third party intending to misuse data to discover which signal line in the second signal line group 33 is conductive in accordance with which address designation signals from the arrangement of the switching devices in the row and column decoders, that is, from a visual layout. In that case, in the conventional address decoder, it is easy to analyze which signal line in the second signal line group 33 is conductive according to certain address designation signals from the arrangement of the switching devices and, therefore, the third party tends to easily read data in the memory cell array and the like. This is not desirable in view of information security.
It is therefore an object of the present invention to provide an address decoder capable of making it more difficult to visually analyze which signal line in the second signal line group is conductive according to inputted address designation signals than in the case of the conventional decoder.
It is another object of the present invention to provide a semiconductor memory which data is difficult to misuse by a third party.
Furthermore, in case of a semiconductor device comprising at least one of a logical product circuit (AND circuit), a logical add circuit (OR circuit) and an inverter circuit, it is preferable that the true structure thereof cannot be easily observed visually to prevent a third party from imitating the semiconductor device and the like. Therefore, it is yet another object of the present innovation to provide a semiconductor device having a structure in which the true structures of at least one of a logical product circuit, a logical add circuit and an inverter circuit are difficult to observe visually.